1. Field of the Invention
The present invention relates generally to methods for fabricating ion implanted microelectronic structures, as employed for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for fabricating shallow ion implanted microelectronic structures, as employed for fabricating microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Ubiquitous within the fabrication of semiconductor integrated circuit microelectronic fabrications is the use of field effect transistor (FET) devices as switching devices within both logic semiconductor integrated circuit microelectronic fabrications and memory semiconductor integrated circuit microelectronic fabrications. Field effect transistor (FET) devices are ubiquitous within the art of semiconductor integrated circuit microelectronic fabrication for use as switching devices within logic semiconductor integrated circuit microelectronic fabrications and memory semiconductor integrated circuit microelectronic fabrications insofar as field effect transistor (FET) devices, in addition to being generally readily fabricated within semiconductor integrated circuit microelectronic fabrications, are also generally readily scalable within semiconductor integrated circuit microelectronic fabrications.
While field effect transistor (FET) devices are thus clearly desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication. In that regard, while semiconductor integrated circuit microelectronic fabrication integration levels have increased and field effect transistor (FET) device dimensions have decreased, it is often difficult in the art of semiconductor integrated circuit microelectronic fabrication to fabricate semiconductor devices, and in particular field effect transistor (FET) devices, simultaneously with decreased dimensions and with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide methods and materials through which there may be fabricated within semiconductor integrated circuit microelectronic fabrications semiconductor devices, and in particular field effect transistor (FET) devices, simultaneously with decreased dimensions and enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various semiconductor device structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication.
Included among the semiconductor device structures and methods for fabrication thereof, but not limiting among the semiconductor device structures and methods for fabrication thereof, are semiconductor device structures and methods for fabrication thereof disclosed within: (1) Lee, in U.S. Pat. No. 6,037,640 (a semiconductor device P-N junction structure formed within a semiconductor substrate, such as may be employed within a source/drain region within a field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication, formed of shallow depth and abrupt dopant transition by employing when fabricating the semiconductor device P-N junction structure within the semiconductor substrate: (1) a dose of a high energy co-implantation ion implanted deeper within the semiconductor substrate in conjunction with a dose of a low energy dopant ion implanted shallower within the semiconductor substrate; followed by (2) a rapid thermal annealing of the semiconductor substrate); and (2) Lee et al., in U.S. Pat. No. 6,051,483 (a semiconductor device P-N junction structure formed within a semiconductor substrate, such as may be employed within a source/drain region within a field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication, formed of shallow depth and abrupt dopant transition by employing when fabricating the semiconductor device P-N junction structure within the semiconductor substrate: (1) a low energy dopant ion implanted within the semiconductor substrate; in conjunction with (2) a microwave energy annealing of the semiconductor substrate).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for fabricating within semiconductor integrated circuit microelectronic fabrications semiconductor devices, and in particular field effect transistor (FET) devices, with decreased dimensions and enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a semiconductor device.
A second object of the present invention is to provide the method for fabricating within the semiconductor integrated circuit microelectronic fabrication the semiconductor device in accord with the first object of the present invention, wherein the semiconductor device is fabricated with decreased dimensions and enhanced performance.
A third object of the present invention is to provide the method for fabricating within the semiconductor integrated circuit microelectronic fabrication the semiconductor device in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by a more specific embodiment of the present invention a method for fabricating a field effect transistor (FET) device.
To practice the more specific embodiment of the method of the present invention, there is first provided a semiconductor substrate having defined therein an active region. There is then formed upon the active region of the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a patterned gate electrode material layer which defines a channel location within the active region of the semiconductor substrate which in turn separates a pair of source/drain locations within the active region of the semiconductor substrate. There is then implanted, while masking the pair of source/drain locations, a first dose of a first dopant into the patterned gate electrode material layer to form a gate electrode. There is also implanted, while not masking the pair of source/drain locations, a second dose of a second dopant into the pair of source/drain locations to form a pair of source/drain regions therein.
A more general embodiment of the present invention provides an analogous method for forming an ion implanted topographic microelectronic structure formed over a substrate employed within a microelectronic fabrication while independently forming an ion implanted structure within the substrate adjacent the ion implanted topographic microelectronic structure.
The present invention provides a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a semiconductor device, and in particular a field effect transistor (FET) device, wherein the semiconductor device, and in particular the field effect transistor (FET) device, is fabricated with decreased dimensions and enhanced performance.
The present invention realizes the foregoing object when fabricating within the semiconductor integrated circuit microelectronic fabrication the field effect transistor (FET) device by: (1) implanting, while masking a pair of source/drain locations within an active region of a semiconductor substrate, a first dose of a first dopant into a patterned gate electrode material layer to form therefrom a gate electrode; and (2) implanting, while not masking the pair of source/drain locations within the active region of the semiconductor substrate, a second dose of a second dopant into the pair of source/drain locations to form a pair of source/drain regions. In particular, by masking the pair of source/drain locations within the active region of the semiconductor substrate when implanting the first dose of the first dopant into the patterned gate electrode material layer to form the gate electrode, the pair of source/drain regions when formed within the pair of source/drain locations may be formed independently and with more controlled ion implantation properties, such as in particular to provide the pair of source/drain regions with a controlled and shallow junction depth.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known and/or readily available in the art of microelectronic fabrication, but employed within the context of specific process limitations to provide the present invention. Since it is thus at least in part a series of specific process limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.